1. Field of the Invention
The present invention relates to integrated circuits (xe2x80x9cICsxe2x80x9d) and, more particularly, to an apparatus and method for providing a reconfigurable Built-in Self-Test (xe2x80x9cBISTxe2x80x9d) engine for testing a reconfigurable memory, such as an on-chip cache in a microprocessor.
2. The Background Art
BIST is one of the methods known to those of ordinary skill in the art for testing memory arrays on an IC for manufacturing defects. This method, commonly known as xe2x80x9cmemory BIST,xe2x80x9d typically uses on-chip logic that generally includes a data pattern generator, an address generator, a comparator (or a signature analyzer) and a finite state machine. Commonly, all of this logic is collectively referred to as xe2x80x9cthe BIST engine.xe2x80x9d As is well known to those of ordinary skill in the art, a class of memory test algorithms, called xe2x80x9cmarch algorithms,xe2x80x9d are commonly used to read and write specific data patterns to the memory under test in specific address sequences. The BIST engine is designed to perform the selected memory test algorithm, and the associated circuitry is designed as an integral part of the IC itself. For the purposes of the present invention, the term xe2x80x9cICxe2x80x9d is used synonymously with the term xe2x80x9cchip,xe2x80x9d and both terms are well-known to those of ordinary skill in the art.
Some modern microprocessors implement both a level-1 (xe2x80x9cL1xe2x80x9d) and a level-2 (xe2x80x9cL2xe2x80x9d) cache directly on the microprocessor IC. One of the ways to test the L2 cache is by using a BIST engine, partly because the L2 cache is not directly accessible or testable via external pins on the microprocessor IC. During IC manufacturing, it is well known to those of ordinary skill in the art to replace some of the faulty rows and/or columns in the L2 cache and other large memories with redundant rows and/or columns to enhance yield. Normally, only relatively few (e.g., two to four) redundant rows and/or columns are provided for repair. If there are any additional manufacturing defects in the memory after all the redundant rows and/or columns available for repair have been used, the IC is deemed to be faulty and typically discarded.
However, in the special case of block-based memory circuits such as L2 caches, some of these xe2x80x9cfaultyxe2x80x9d ICs can be productized into ICs with a smaller level 2 cache. Because the design of an L2 cache is typically based on blocks, if the blocks corresponding to half of the address space of the cache are not faulty, the IC may still be marketed as a good, working microprocessor, but having a smaller cache. For example, a microprocessor nominally having a 512 KB L2 cache may be marketed as microprocessor having a 256 KB L2 cache, with the faulty half of the L2 cache deactivated. One mechanism known to those of ordinary skill in the art for de-activating the faulty half of the L2 cache consists of either a hardware programmable or software programmable fuse (of which there may be more than one) that can be set after the die is manufactured. Without limitation, in the hardware programmable version of the fuse, the fuse is blown using a laser or xe2x80x9ce-fusexe2x80x9d (which is typically implemented by driving high current through the device pins to blow the fuse). Without limitation, in the software programmable version of the fuse, it is programmed by writing to a programmable register (which is typically xe2x80x9cone-time programmable,xe2x80x9d such as an EPROM or flash memory). Once the memory structure is tested and the faulty half of the memory device is identified, the fuse is programmed to de-activate the faulty half and to reconfigure the memory into a smaller size. Even though it is not practically useful, a memory can be reconfigured to one-fourth, one-eight, etc. (inverse powers of two).
If the reconfigured memory must be retested, the original BIST engine design cannot be used without modification, since it is designed to run the march test algorithm on the original (e.g., 512 KB) L2 cache. The memory BIST algorithm, if executed using the original BIST engine, would flag the cache as faulty, since the original BIST engine is designed to test the entire memory. Moreover, it will unnecessarily test an area of the cache that has been determined not to be a part of the functioning microprocessor.
Thus, what is needed is a reconfigurable BIST engine that is automatically reconfigured whenever the memory being tested is reconfigured, such that the reconfigured memory can be automatically tested. Unfortunately, no such reconfigurable BIST engine is currently available. The present invention addresses this and other problems. These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and in the associated figures.
A reconfigurable built-in self-test (xe2x80x9cBISTxe2x80x9d) engine for testing a reconfigurable memory is disclosed. The BIST engine executes a test on a memory for detecting faults. If the memory under test fails the test executed by the BIST engine, a decision is made depending on whether it is possible to reconfigure the memory under test. If memory reconfiguration is possible, the memory under test is reconfigured, such as by disabling the bad half of the memory under test. Once the memory under test is reconfigured, the BIST engine is also reconfigured in a manner appropriate for the type of BIST enginexe2x80x94centralized or distributed. In the case of a centralized BIST engine, a centralized BIST controller is modified to generate addresses corresponding only to the good half of the memory under test. In the case of a distributed BIST engine, a BIST meta-controller is modified to disable distributed BIST engines corresponding to memory sub-blocks in the bad half of the memory under test and to ignore error signals reported by any such disabled distributed BIST engines. The reconfigured memory under test is then tested with the reconfigured BIST engine.